The performance of processors in contemporary server systems has been significantly improved. However, the response of memory access with a CPU is late, and this is a bottleneck to performance improvement. A processor has a cache memory in addition to a CPU. When memory access from the CPU is generated, the cache memory is initially checked, and where a cache hit is determined, the cache memory is accessed. Where a cache miss is determined, the main memory is accessed. The access to the cache memory is 100 times to 300 times faster than that to the main memory. Therefore, in order to improve the performance of memory access with a CPU, it is important to maximize the possibility of cache hits and generate few accesses to the main memory as soon as possible.
A cache hit rate generally rises as the cache size increases. However, where the cache size is comparatively small, the cache hit rate increases significantly with the increase in the cache size, but where the cache size increases to a certain degree; the cache hit rate does not increase anymore despite the increase in the cache size.
Meanwhile, following the transition to multitasking, the processors execute a plurality of processes simultaneously or alternately. For this reason, data on a plurality of processes are stored in the cache memory, an area of the cache memory that has been used by a first process is used by a second process, which is different from the first process, and the data of the first process are pushed out of the cache memory. For this reason, where the first process is thereafter restarted, a cache mishit frequently occurs. Therefore, in the architecture where the same cache memory is shared by all of the processes, it is needed to improve somehow the cache memory control in order to increase the cache hit rate.
The technique of allocating a dedicated cache area to specific processing has been suggested as an example of such improvement. Such technique is described, for example, in the patent documents listed hereinbelow. As a result, the memory process of the specific processing is limited to the dedicated cache area, and therefore the occurrence of cache mishits in a shared cache area is suppressed.
The followings documents relate to the cache memory control program.    Patent Document 1: Japanese Laid-open Patent Publication No. 2004-133931    Patent Document 2: Japanese National Publication of International Patent Application No. 2009-518754    Patent Document 3: Japanese Laid-open Patent Publication No. 2002-7213    Patent Document 4: Japanese Laid-open Patent Publication No. 2006-4203    Patent Document 5: Japanese Laid-open Patent Publication No. 02-18644    Patent Document 6: Japanese Laid-open Patent Publication No. 2009-211649    Patent Document 7: Japanese Laid-open Patent Publication No. 2009-163450